The use of the charge redistribution DAC, which relies on capacitive element matching, limits the achievable effective resolution of nowadays Successive Approximation Register (SAR) ADCs below about 13 effective bits. To overcome this limitation, this paper discusses the implementation of an incremental sigma delta (I-SD) DAC in the feedback path of a 16-bit SAR ADC. The proposed DAC uses an intrinsically linear one-bit output from a digital SD modulator, which is passed to an analog reconstruction filter. The filter architecture including an FIR part and active integrators is implemented on transistor level. The circuit is implemented using TSMC's 40nm CMOS technology. The I-SD-DAC achieves 100 dB SFDR at a sampling frequency of 500 kHz. A behavioral level simulation of a 16-bit SAR ADC loop employing the designed schematic I-SD-DAC loop achieves an SFDR of 96.2 dB and an SNDR of 83.5dB with 34.18 kS/s.
%0 Conference Paper
%1 7251362
%A AlMarashli, A.
%A Anders, J.
%A Ortmanns, M.
%B 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
%D 2015
%K SAR ADC from:jens.anders
%P 172-175
%R 10.1109/PRIME.2015.7251362
%T Design study on a SAR ADC using an incremental ΣΔ-DAC
%U https://ieeexplore.ieee.org/document/7251362/
%X The use of the charge redistribution DAC, which relies on capacitive element matching, limits the achievable effective resolution of nowadays Successive Approximation Register (SAR) ADCs below about 13 effective bits. To overcome this limitation, this paper discusses the implementation of an incremental sigma delta (I-SD) DAC in the feedback path of a 16-bit SAR ADC. The proposed DAC uses an intrinsically linear one-bit output from a digital SD modulator, which is passed to an analog reconstruction filter. The filter architecture including an FIR part and active integrators is implemented on transistor level. The circuit is implemented using TSMC's 40nm CMOS technology. The I-SD-DAC achieves 100 dB SFDR at a sampling frequency of 500 kHz. A behavioral level simulation of a 16-bit SAR ADC loop employing the designed schematic I-SD-DAC loop achieves an SFDR of 96.2 dB and an SNDR of 83.5dB with 34.18 kS/s.
@inproceedings{7251362,
abstract = {The use of the charge redistribution DAC, which relies on capacitive element matching, limits the achievable effective resolution of nowadays Successive Approximation Register (SAR) ADCs below about 13 effective bits. To overcome this limitation, this paper discusses the implementation of an incremental sigma delta (I-SD) DAC in the feedback path of a 16-bit SAR ADC. The proposed DAC uses an intrinsically linear one-bit output from a digital SD modulator, which is passed to an analog reconstruction filter. The filter architecture including an FIR part and active integrators is implemented on transistor level. The circuit is implemented using TSMC's 40nm CMOS technology. The I-SD-DAC achieves 100 dB SFDR at a sampling frequency of 500 kHz. A behavioral level simulation of a 16-bit SAR ADC loop employing the designed schematic I-SD-DAC loop achieves an SFDR of 96.2 dB and an SNDR of 83.5dB with 34.18 kS/s.},
added-at = {2020-10-12T15:53:36.000+0200},
author = {{AlMarashli}, A. and {Anders}, J. and {Ortmanns}, M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/20f6288d639c4840c6ae9d564fe17d327/iis},
booktitle = {2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)},
doi = {10.1109/PRIME.2015.7251362},
interhash = {5bd0bdd057f90dae996f88db4940ec97},
intrahash = {0f6288d639c4840c6ae9d564fe17d327},
keywords = {SAR ADC from:jens.anders},
month = {June},
pages = {172-175},
timestamp = {2020-10-12T13:53:36.000+0200},
title = {Design study on a SAR ADC using an incremental ΣΔ-DAC},
url = {https://ieeexplore.ieee.org/document/7251362/},
year = 2015
}
