%0 Conference Paper %1 conf/ngcas/FanWXFLZDLH18 %A Fan, Hua %A Wang, Chen %A Xiong, Hailiang %A Feng, Quanyuan %A Li, Dagang %A Zhang, Kelin %A Diao, Xiaopeng %A Lin, Lishuang %A Heidari, Hadi %B NGCAS %D 2018 %I IEEE %K dblp %P 1-4 %T A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). %U http://dblp.uni-trier.de/db/conf/ngcas/ngcas2018.html#FanWXFLZDLH18 %@ 978-1-5386-7681-3

@inproceedings{conf/ngcas/FanWXFLZDLH18, added-at = {2018-12-20T00:00:00.000+0100}, author = {Fan, Hua and Wang, Chen and Xiong, Hailiang and Feng, Quanyuan and Li, Dagang and Zhang, Kelin and Diao, Xiaopeng and Lin, Lishuang and Heidari, Hadi}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2ef5a52b504d9f099233a049d95c317c6/dblp}, booktitle = {NGCAS}, crossref = {conf/ngcas/2018}, ee = {https://doi.org/10.1109/NGCAS.2018.8572141}, interhash = {f5bcb88171877ae07f6d3a5f780c757a}, intrahash = {ef5a52b504d9f099233a049d95c317c6}, isbn = {978-1-5386-7681-3}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-09-27T15:13:04.000+0200}, title = {A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).}, url = {http://dblp.uni-trier.de/db/conf/ngcas/ngcas2018.html#FanWXFLZDLH18}, year = 2018 }