%0 Journal Article %1 journals/tcas/ChengYLYU14 %A Cheng, Chung-Chao %A Yang, Jeng-Da %A Lee, Huang-Chang %A Yang, Chia-Hsiang %A Ueng, Yeong-Luh %D 2014 %J IEEE Trans. on Circuits and Systems %K dblp %N 9 %P 2738-2746 %T A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI61.html#ChengYLYU14 %V 61-I

@article{journals/tcas/ChengYLYU14, added-at = {2014-10-08T00:00:00.000+0200}, author = {Cheng, Chung-Chao and Yang, Jeng-Da and Lee, Huang-Chang and Yang, Chia-Hsiang and Ueng, Yeong-Luh}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/29b2565068fcb8db27205aa14b9e7cfe9/dblp}, ee = {http://dx.doi.org/10.1109/TCSI.2014.2312479}, interhash = {e4ed584381b8e690100cc4bc69a7885c}, intrahash = {9b2565068fcb8db27205aa14b9e7cfe9}, journal = {IEEE Trans. on Circuits and Systems}, keywords = {dblp}, number = 9, pages = {2738-2746}, timestamp = {2016-02-02T02:20:27.000+0100}, title = {A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI61.html#ChengYLYU14}, volume = {61-I}, year = 2014 }