%0 Conference Paper %1 conf/vlsid/JoshiKWNC07 %A Joshi, Rajiv V. %A Kim, Keunwoo %A Williams, Richard Q. %A Nowak, Edward J. %A Chuang, Ching-Te %B VLSI Design %D 2007 %I IEEE Computer Society %K dblp %P 665-672 %T A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#JoshiKWNC07 %@ 0-7695-2762-0

@inproceedings{conf/vlsid/JoshiKWNC07, added-at = {2015-04-20T00:00:00.000+0200}, author = {Joshi, Rajiv V. and Kim, Keunwoo and Williams, Richard Q. and Nowak, Edward J. and Chuang, Ching-Te}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2ebd4d62235ee104a9e454900951064d4/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2007}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.182}, interhash = {e3eb28a1230b558c0bfa938601b35f18}, intrahash = {ebd4d62235ee104a9e454900951064d4}, isbn = {0-7695-2762-0}, keywords = {dblp}, pages = {665-672}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T11:08:40.000+0100}, title = {A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#JoshiKWNC07}, year = 2007 }