%0 Conference Paper
%1 conf/reconfig/AmmendolaBFCLPRSTV13
%A Ammendola, Roberto
%A Biagioni, Andrea
%A Frezza, Ottorino
%A Cicero, Francesca Lo
%A Lonardo, Alessandro
%A Paolucci, Pier Stanislao
%A Rossetti, Davide
%A Simula, Francesco
%A Tosoratto, Laura
%A Vicini, Piero
%B ReConFig
%D 2013
%I IEEE
%K dblp
%P 1-6
%T Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.
%U http://dblp.uni-trier.de/db/conf/reconfig/reconfig2013.html#AmmendolaBFCLPRSTV13
%@ 978-1-4799-2079-2
@inproceedings{conf/reconfig/AmmendolaBFCLPRSTV13,
added-at = {2014-02-17T00:00:00.000+0100},
author = {Ammendola, Roberto and Biagioni, Andrea and Frezza, Ottorino and Cicero, Francesca Lo and Lonardo, Alessandro and Paolucci, Pier Stanislao and Rossetti, Davide and Simula, Francesco and Tosoratto, Laura and Vicini, Piero},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/206e8979fa16b774150486604d304278c/dblp},
booktitle = {ReConFig},
crossref = {conf/reconfig/2013},
ee = {http://dx.doi.org/10.1109/ReConFig.2013.6732275},
interhash = {dfcaa27632a099f329dad27d8fe21ca6},
intrahash = {06e8979fa16b774150486604d304278c},
isbn = {978-1-4799-2079-2},
keywords = {dblp},
pages = {1-6},
publisher = {IEEE},
timestamp = {2016-02-02T12:08:15.000+0100},
title = {Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.},
url = {http://dblp.uni-trier.de/db/conf/reconfig/reconfig2013.html#AmmendolaBFCLPRSTV13},
year = 2013
}