%0 Thesis %1 phd/dnb/Hartmann99 %A Hartmann, Stephan %D 1999 %I Cuvillier %K dblp %P 1-142 %T Layout problems in VLSI circuit design. %@ 978-3-89712-577-3

@phdthesis{phd/dnb/Hartmann99, added-at = {2019-03-14T00:00:00.000+0100}, author = {Hartmann, Stephan}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/278343e56f36916b5d4ed12d347b8ae39/dblp}, ee = {http://d-nb.info/957200625}, interhash = {dd8b0db2e5f782af176cbaec16a01c42}, intrahash = {78343e56f36916b5d4ed12d347b8ae39}, isbn = {978-3-89712-577-3}, keywords = {dblp}, pages = {1-142}, publisher = {Cuvillier}, school = {Technical University of Berlin, Germany}, timestamp = {2019-09-27T12:25:08.000+0200}, title = {Layout problems in VLSI circuit design.}, year = 1999 }