%0 Conference Paper %1 conf/fpga/BsoulW12 %A Bsoul, Assem A. M. %A Wilton, Steven J. E. %B FPGA %D 2012 %E Compton, Katherine %E Hutchings, Brad L. %I ACM %K dblp %P 245-254 %T A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. %U http://dblp.uni-trier.de/db/conf/fpga/fpga2012.html#BsoulW12 %@ 978-1-4503-1155-7

@inproceedings{conf/fpga/BsoulW12, added-at = {2018-11-06T00:00:00.000+0100}, author = {Bsoul, Assem A. M. and Wilton, Steven J. E.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2274732d061b8cfdc6df3ed2b1906ff5c/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2012}, editor = {Compton, Katherine and Hutchings, Brad L.}, ee = {https://doi.org/10.1145/2145694.2145737}, interhash = {d946653ab9b47520d2d54abbbbfa57f3}, intrahash = {274732d061b8cfdc6df3ed2b1906ff5c}, isbn = {978-1-4503-1155-7}, keywords = {dblp}, pages = {245-254}, publisher = {ACM}, timestamp = {2019-09-27T13:25:36.000+0200}, title = {A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2012.html#BsoulW12}, year = 2012 }