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%0 Conference Paper
%1 conf/glvlsi/JohannesCM92
%A Johannes, P.
%A Claesen, Luc J. M.
%A Man, Hugo De
%B Great Lakes Symposium on VLSI
%D 1992
%I IEEE
%K dblp
%P 4-8
%T On the use of hierarchy in timing verification with statically sensitizable paths.
%U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1992.html#JohannesCM92
%@ 0-8186-2610-0
@inproceedings{conf/glvlsi/JohannesCM92,
added-at = {2014-10-01T00:00:00.000+0200},
author = {Johannes, P. and Claesen, Luc J. M. and Man, Hugo De},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/249d6671f16ae8b1f5d8524ccc37dc181/dblp},
booktitle = {Great Lakes Symposium on VLSI},
crossref = {conf/glvlsi/1992},
ee = {http://dx.doi.org/10.1109/GLSV.1992.218372},
interhash = {d696ffa0c3da217758ea57dfc07526f9},
intrahash = {49d6671f16ae8b1f5d8524ccc37dc181},
isbn = {0-8186-2610-0},
keywords = {dblp},
pages = {4-8},
publisher = {IEEE},
timestamp = {2016-02-02T12:50:05.000+0100},
title = {On the use of hierarchy in timing verification with statically sensitizable paths.},
url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1992.html#JohannesCM92},
year = 1992
}
