@article{journals/jssc/KangJKKCKRKLKLY17,
added-at = {2017-01-25T00:00:00.000+0100},
author = {Kang, Dongku and Jeong, Woopyo and Kim, Chulbum and Kim, Doo-Hyun and Cho, Yong-Sung and Kang, Kyung-Tae and Ryu, Jinho and Kang, Kyung-Min and Lee, Sungyeon and Kim, Wandong and Lee, Hanjun and Yu, Jaedoeg and Choi, Nayoung and Jang, Dong-Su and Lee, Cheon An and Min, Young-Sun and Kim, Moosung and Park, Ansoo and Son, Jae-Ick and Kim, In-Mo and Kwak, Pansuk and Jung, Bong-Kil and Lee, Doosub and Kim, Hyunggon and Ihm, Jeong-Don and Byeon, Dae-Seok and Lee, Jin-Yup and Park, Ki-Tae and Kyung, Kyehyun},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/24ee2337b31897436a97f97c3d40d8115/dblp},
ee = {http://dx.doi.org/10.1109/JSSC.2016.2604297},
interhash = {d26f30c7fb6dc0e8418f044d11d2beec},
intrahash = {4ee2337b31897436a97f97c3d40d8115},
journal = {J. Solid-State Circuits},
keywords = {dblp},
number = 1,
pages = {210-217},
timestamp = {2017-01-26T10:32:41.000+0100},
title = {256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc52.html#KangJKKCKRKLKLY17},
volume = 52,
year = 2017
}