%0 Conference Paper %1 conf/rtas/YanZ08 %A Yan, Jun %A Zhang, Wei %B IEEE Real-Time and Embedded Technology and Applications Symposium %D 2008 %I IEEE Computer Society %K dblp %P 80-89 %T WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. %U http://dblp.uni-trier.de/db/conf/rtas/rtas2008.html#YanZ08 %@ 978-0-7695-3146-5

@inproceedings{conf/rtas/YanZ08, added-at = {2014-10-01T00:00:00.000+0200}, author = {Yan, Jun and Zhang, Wei}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2a4a2c547d716ffaff917ea76296c5468/dblp}, booktitle = {IEEE Real-Time and Embedded Technology and Applications Symposium}, crossref = {conf/rtas/2008}, ee = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2008.6}, interhash = {cdcf30df91a789f0db51b7c45ad54c2a}, intrahash = {a4a2c547d716ffaff917ea76296c5468}, isbn = {978-0-7695-3146-5}, keywords = {dblp}, pages = {80-89}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T13:04:00.000+0100}, title = {WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches.}, url = {http://dblp.uni-trier.de/db/conf/rtas/rtas2008.html#YanZ08}, year = 2008 }