%0 Journal Article %1 journals/tvlsi/ChenLY16 %A Chen, Pai-Yu %A Li, Zhiwei %A Yu, Shimeng %D 2016 %J IEEE Trans. VLSI Syst. %K dblp %N 12 %P 3460-3467 %T Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#ChenLY16 %V 24

@article{journals/tvlsi/ChenLY16, added-at = {2016-11-25T00:00:00.000+0100}, author = {Chen, Pai-Yu and Li, Zhiwei and Yu, Shimeng}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/21d38675e6c6827d660220fab29fab6ce/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2016.2553123}, interhash = {cd459b9afae54df7673e030435d36a5f}, intrahash = {1d38675e6c6827d660220fab29fab6ce}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 12, pages = {3460-3467}, timestamp = {2016-11-26T10:32:05.000+0100}, title = {Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#ChenLY16}, volume = 24, year = 2016 }