%0 Journal Article %1 journals/tcad/DekkerBT90 %A Dekker, Rob %A Beenker, Frans P. M. %A Thijssen, Loek %D 1990 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 6 %P 567-572 %T A realistic fault model and test algorithms for static random access memories. %U http://dblp.uni-trier.de/db/journals/tcad/tcad9.html#DekkerBT90 %V 9

@article{journals/tcad/DekkerBT90, added-at = {2016-03-18T00:00:00.000+0100}, author = {Dekker, Rob and Beenker, Frans P. M. and Thijssen, Loek}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/29aceb556842d3cd27e2839e30911867a/dblp}, ee = {http://dx.doi.org/10.1109/43.55188}, interhash = {c203072b9cb7ff23f977bdebc5d12810}, intrahash = {9aceb556842d3cd27e2839e30911867a}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 6, pages = {567-572}, timestamp = {2016-03-19T10:33:23.000+0100}, title = {A realistic fault model and test algorithms for static random access memories.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad9.html#DekkerBT90}, volume = 9, year = 1990 }