%0 Journal Article %1 journals/tcad/OdabasiogluCP98 %A Odabasioglu, Altan %A Celik, Mustafa %A Pileggi, Lawrence T. %D 1998 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 8 %P 645-654 %T PRIMA: passive reduced-order interconnect macromodeling algorithm. %U http://dblp.uni-trier.de/db/journals/tcad/tcad17.html#OdabasiogluCP98 %V 17

@article{journals/tcad/OdabasiogluCP98, added-at = {2019-06-02T00:00:00.000+0200}, author = {Odabasioglu, Altan and Celik, Mustafa and Pileggi, Lawrence T.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d58508fc29e74081bda8d9beb6f5aea8/dblp}, ee = {https://www.wikidata.org/entity/Q59509197}, interhash = {b2a53023db8fa6655e926c6254a6365e}, intrahash = {d58508fc29e74081bda8d9beb6f5aea8}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 8, pages = {645-654}, timestamp = {2019-09-27T08:26:59.000+0200}, title = {PRIMA: passive reduced-order interconnect macromodeling algorithm.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad17.html#OdabasiogluCP98}, volume = 17, year = 1998 }