%0 Journal Article %1 journals/tvlsi/ChiouCC09 %A Chiou, De-Shiuan %A Chen, Shih-Hsin %A Chang, Shih-Chieh %D 2009 %J IEEE Trans. VLSI Syst. %K dblp %N 9 %P 1330-1334 %T Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi17.html#ChiouCC09 %V 17

@article{journals/tvlsi/ChiouCC09, added-at = {2010-11-16T00:00:00.000+0100}, author = {Chiou, De-Shiuan and Chen, Shih-Hsin and Chang, Shih-Chieh}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23e62fdaccd6490b6206b4509bf660eba/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2008.2001247}, interhash = {a997405a8c852c98b6e337ba8e679e20}, intrahash = {3e62fdaccd6490b6206b4509bf660eba}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 9, pages = {1330-1334}, timestamp = {2016-02-02T02:13:08.000+0100}, title = {Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi17.html#ChiouCC09}, volume = 17, year = 2009 }