%0 Journal Article %1 journals/tvlsi/NajafiLRB18 %A Najafi, M. Hassan %A Lilja, David J. %A Riedel, Marc D. %A Bazargan, Kia %D 2018 %J IEEE Trans. VLSI Syst. %K dblp %N 8 %P 1471-1480 %T Low-Cost Sorting Network Circuits Using Unary Processing. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#NajafiLRB18 %V 26

@article{journals/tvlsi/NajafiLRB18, added-at = {2018-08-11T00:00:00.000+0200}, author = {Najafi, M. Hassan and Lilja, David J. and Riedel, Marc D. and Bazargan, Kia}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/21e8d029dda1fb9a4e98d0734d2401cab/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2822300}, interhash = {a194bad2d49b8923ad6ce405fa34f149}, intrahash = {1e8d029dda1fb9a4e98d0734d2401cab}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 8, pages = {1471-1480}, timestamp = {2019-09-27T06:53:33.000+0200}, title = {Low-Cost Sorting Network Circuits Using Unary Processing.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#NajafiLRB18}, volume = 26, year = 2018 }