%0 Conference Paper %1 conf/vlsid/SaveNP12 %A Save, Yogesh Dilip %A Narayanan, H. %A Patkar, Sachin B. %B VLSI Design %D 2012 %E Agrawal, Vishwani D. %E Chakradhar, Srimat T. %I IEEE Computer Society %K dblp %P 400-405 %T Two Graph Based Circuit Simulator for PDE-Electrical Analogy. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2012.html#SaveNP12 %@ 978-1-4673-0438-2

@inproceedings{conf/vlsid/SaveNP12, added-at = {2015-04-20T00:00:00.000+0200}, author = {Save, Yogesh Dilip and Narayanan, H. and Patkar, Sachin B.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/281b2bbb1c84d7ee16d39fb9201239472/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2012}, editor = {Agrawal, Vishwani D. and Chakradhar, Srimat T.}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2012.104}, interhash = {9afc0b6df44cf41b76da6df363c3a45f}, intrahash = {81b2bbb1c84d7ee16d39fb9201239472}, isbn = {978-1-4673-0438-2}, keywords = {dblp}, pages = {400-405}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T11:08:31.000+0100}, title = {Two Graph Based Circuit Simulator for PDE-Electrical Analogy.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2012.html#SaveNP12}, year = 2012 }