%0 Journal Article %1 journals/jetc/ChenCH16 %A Chen, Yi-Hang %A Chen, Jian-Yu %A Huang, Juinn-Dar %D 2016 %J JETC %K dblp %N 4 %P 37:1-37:15 %T Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints. %U http://dblp.uni-trier.de/db/journals/jetc/jetc12.html#ChenCH16 %V 12

@article{journals/jetc/ChenCH16, added-at = {2018-11-06T00:00:00.000+0100}, author = {Chen, Yi-Hang and Chen, Jian-Yu and Huang, Juinn-Dar}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/265d18f0195c5822c7187447c79008136/dblp}, ee = {https://doi.org/10.1145/2906360}, interhash = {93291e3f3a4a30fb64a9aa6c762fe1e7}, intrahash = {65d18f0195c5822c7187447c79008136}, journal = {JETC}, keywords = {dblp}, number = 4, pages = {37:1-37:15}, timestamp = {2019-09-27T08:51:40.000+0200}, title = {Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints.}, url = {http://dblp.uni-trier.de/db/journals/jetc/jetc12.html#ChenCH16}, volume = 12, year = 2016 }