%0 Journal Article %1 journals/tvlsi/LeeH18 %A Lee, Yu-Hsuan %A Huang, Meng-Ren %D 2018 %J IEEE Trans. VLSI Syst. %K dblp %N 11 %P 2553-2566 %T Algorithm and Architecture Design of a Hardware-Efficient Frame Rate Upconversion Engine. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#LeeH18 %V 26

@article{journals/tvlsi/LeeH18, added-at = {2018-11-02T00:00:00.000+0100}, author = {Lee, Yu-Hsuan and Huang, Meng-Ren}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/272288c2937354c88f708c54715195523/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2849438}, interhash = {90ddf7c434836ed4e06f7e53397c1476}, intrahash = {72288c2937354c88f708c54715195523}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 11, pages = {2553-2566}, timestamp = {2019-09-27T06:53:36.000+0200}, title = {Algorithm and Architecture Design of a Hardware-Efficient Frame Rate Upconversion Engine.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#LeeH18}, volume = 26, year = 2018 }