%0 Journal Article %1 journals/tvlsi/ChakrabartyH95 %A Chakrabarty, Krishnendu %A Hayes, John P. %D 1995 %J IEEE Trans. VLSI Syst. %K dblp %N 1 %P 72-83 %T Cumulative balance testing of logic circuits. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi3.html#ChakrabartyH95 %V 3

@article{journals/tvlsi/ChakrabartyH95, added-at = {2016-03-15T00:00:00.000+0100}, author = {Chakrabarty, Krishnendu and Hayes, John P.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/20954b2fb5df459aedceefa209eb77fae/dblp}, ee = {http://dx.doi.org/10.1109/92.365455}, interhash = {8b9a6646c625918f0ff16fde6bcb488f}, intrahash = {0954b2fb5df459aedceefa209eb77fae}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 1, pages = {72-83}, timestamp = {2016-03-16T10:31:54.000+0100}, title = {Cumulative balance testing of logic circuits.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi3.html#ChakrabartyH95}, volume = 3, year = 1995 }