%0 Journal Article %1 journals/tvlsi/DevadasKMW94 %A Devadas, Srinivas %A Keutzer, Kurt %A Malik, Sharad %A Wang, Albert R. %D 1994 %J IEEE Trans. VLSI Syst. %K dblp %N 3 %P 333-342 %T Certified timing verification and the transition delay of a logic circuit. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi2.html#DevadasKMW94 %V 2

@article{journals/tvlsi/DevadasKMW94, added-at = {2016-03-15T00:00:00.000+0100}, author = {Devadas, Srinivas and Keutzer, Kurt and Malik, Sharad and Wang, Albert R.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2e42af64a005ac7a75f5e63234c0a9cec/dblp}, ee = {http://dx.doi.org/10.1109/92.311642}, interhash = {8acca399424cbb3637d30e51734298ef}, intrahash = {e42af64a005ac7a75f5e63234c0a9cec}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 3, pages = {333-342}, timestamp = {2016-03-16T10:31:54.000+0100}, title = {Certified timing verification and the transition delay of a logic circuit.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi2.html#DevadasKMW94}, volume = 2, year = 1994 }