%0 Journal Article %1 journals/integration/MullerSGWB06 %A Müller, Matthias %A Simon, Sven %A Gryska, Holger %A Wortmann, Andreas %A Buch, Steffen %D 2006 %J Integration %K dblp %N 2 %P 131-155 %T Low power synthesizable register files for processor and IP cores. %U http://dblp.uni-trier.de/db/journals/integration/integration39.html#MullerSGWB06 %V 39

@article{journals/integration/MullerSGWB06, added-at = {2007-01-17T00:00:00.000+0100}, author = {Müller, Matthias and Simon, Sven and Gryska, Holger and Wortmann, Andreas and Buch, Steffen}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/265cd4365ea56e144bb0dba36e8195e52/dblp}, ee = {http://dx.doi.org/10.1016/j.vlsi.2004.08.001}, interhash = {88e28071e5af3f5ef7cd697079ca1e25}, intrahash = {65cd4365ea56e144bb0dba36e8195e52}, journal = {Integration}, keywords = {dblp}, number = 2, pages = {131-155}, timestamp = {2016-02-02T09:23:34.000+0100}, title = {Low power synthesizable register files for processor and IP cores.}, url = {http://dblp.uni-trier.de/db/journals/integration/integration39.html#MullerSGWB06}, volume = 39, year = 2006 }