%0 Journal Article %1 journals/tvlsi/ChouKW11 %A Chou, Yung-Fa %A Kwai, Ding-Ming %A Wu, Cheng-Wen %D 2011 %J IEEE Trans. VLSI Syst. %K dblp %N 8 %P 1346-1356 %T Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#ChouKW11 %V 19

@article{journals/tvlsi/ChouKW11, added-at = {2011-08-08T00:00:00.000+0200}, author = {Chou, Yung-Fa and Kwai, Ding-Ming and Wu, Cheng-Wen}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/27e2aa74916823dca44342db920763e47/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2010.2051466}, interhash = {843a7c7104a33fc2fa2d693ef745b9cc}, intrahash = {7e2aa74916823dca44342db920763e47}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 8, pages = {1346-1356}, timestamp = {2016-02-02T02:13:23.000+0100}, title = {Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#ChouKW11}, volume = 19, year = 2011 }