%0 Journal Article %1 journals/tvlsi/SjogrenM00 %A Sjogren, Allen E. %A Myers, Chris J. %D 2000 %J IEEE Trans. VLSI Syst. %K dblp %N 5 %P 573-583 %T Interfacing synchronous and asynchronous modules within a high-speed pipeline. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi8.html#SjogrenM00 %V 8

@article{journals/tvlsi/SjogrenM00, added-at = {2019-06-02T00:00:00.000+0200}, author = {Sjogren, Allen E. and Myers, Chris J.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2112360c3ebf5828492940f064f1189de/dblp}, ee = {https://www.wikidata.org/entity/Q59859620}, interhash = {76edcb1e517eadab15eb83f47ea7748b}, intrahash = {112360c3ebf5828492940f064f1189de}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 5, pages = {573-583}, timestamp = {2019-09-27T06:53:36.000+0200}, title = {Interfacing synchronous and asynchronous modules within a high-speed pipeline.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi8.html#SjogrenM00}, volume = 8, year = 2000 }