%0 Conference Paper %1 conf/date/ChenCH14 %A Chen, Yi-Hang %A Chen, Jian-Yu %A Huang, Juinn-Dar %B DATE %D 2014 %E Fettweis, Gerhard %E Nebel, Wolfgang %I European Design and Automation Association %K dblp %P 1-4 %T Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints. %U http://dblp.uni-trier.de/db/conf/date/date2014.html#ChenCH14 %@ 978-3-9815370-2-4

@inproceedings{conf/date/ChenCH14, added-at = {2015-11-10T00:00:00.000+0100}, author = {Chen, Yi-Hang and Chen, Jian-Yu and Huang, Juinn-Dar}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2de61f44f0438c1d66ceaf7654cb8a0fe/dblp}, booktitle = {DATE}, crossref = {conf/date/2014}, editor = {Fettweis, Gerhard and Nebel, Wolfgang}, ee = {http://dl.acm.org/citation.cfm?id=2616756}, interhash = {6f5f03251077a573e97540ff332fbf64}, intrahash = {de61f44f0438c1d66ceaf7654cb8a0fe}, isbn = {978-3-9815370-2-4}, keywords = {dblp}, pages = {1-4}, publisher = {European Design and Automation Association}, timestamp = {2016-02-02T13:24:19.000+0100}, title = {Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints.}, url = {http://dblp.uni-trier.de/db/conf/date/date2014.html#ChenCH14}, year = 2014 }