%0 Journal Article %1 journals/tvlsi/MajumdarV93 %A Majumdar, Amitava %A Vrudhula, Sarma B. K. %D 1993 %J IEEE Trans. VLSI Syst. %K dblp %N 3 %P 365-379 %T Analysis of signal probability in logic circuits using stochastic models. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi1.html#MajumdarV93 %V 1

@article{journals/tvlsi/MajumdarV93, added-at = {2016-03-15T00:00:00.000+0100}, author = {Majumdar, Amitava and Vrudhula, Sarma B. K.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/208b5ed4bffbbc83ff44ca5e16d7abbfe/dblp}, ee = {http://dx.doi.org/10.1109/92.238448}, interhash = {6f49a0d606fc80b3e34ec4fddf014fb0}, intrahash = {08b5ed4bffbbc83ff44ca5e16d7abbfe}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 3, pages = {365-379}, timestamp = {2016-03-16T10:32:04.000+0100}, title = {Analysis of signal probability in logic circuits using stochastic models.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi1.html#MajumdarV93}, volume = 1, year = 1993 }