%0 Journal Article %1 journals/rts/WuPG16 %A Wu, Zheng Pei %A Pellizzoni, Rodolfo %A Guo, Danlu %D 2016 %J Real-Time Systems %K dblp %N 6 %P 761-807 %T A composable worst case latency analysis for multi-rank DRAM devices under open row policy. %U http://dblp.uni-trier.de/db/journals/rts/rts52.html#WuPG16 %V 52

@article{journals/rts/WuPG16, added-at = {2016-08-19T00:00:00.000+0200}, author = {Wu, Zheng Pei and Pellizzoni, Rodolfo and Guo, Danlu}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/297ae8ac6b21dded4b3c47d46738db718/dblp}, ee = {http://dx.doi.org/10.1007/s11241-016-9253-4}, interhash = {6e52d39de5235694079cf5ba4f20e189}, intrahash = {97ae8ac6b21dded4b3c47d46738db718}, journal = {Real-Time Systems}, keywords = {dblp}, number = 6, pages = {761-807}, timestamp = {2016-08-20T09:32:11.000+0200}, title = {A composable worst case latency analysis for multi-rank DRAM devices under open row policy.}, url = {http://dblp.uni-trier.de/db/journals/rts/rts52.html#WuPG16}, volume = 52, year = 2016 }