%0 Journal Article %1 journals/chinaf/WangLYZCYW13 %A Wang, Yansheng %A Liu, Leibo %A Yin, Shouyi %A Zhu, Min %A Cao, Peng %A Yang, Jun %A Wei, Shaojun %D 2013 %J SCIENCE CHINA Information Sciences %K dblp %N 11 %P 1-20 %T Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. %U http://dblp.uni-trier.de/db/journals/chinaf/chinaf56.html#WangLYZCYW13 %V 56

@article{journals/chinaf/WangLYZCYW13, added-at = {2013-12-18T00:00:00.000+0100}, author = {Wang, Yansheng and Liu, Leibo and Yin, Shouyi and Zhu, Min and Cao, Peng and Yang, Jun and Wei, Shaojun}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2e2e2b24e23618c957142da0474668f69/dblp}, ee = {http://dx.doi.org/10.1007/s11432-013-4842-5}, interhash = {16dff70b13d6e3afea7d2af56a63fb01}, intrahash = {e2e2b24e23618c957142da0474668f69}, journal = {SCIENCE CHINA Information Sciences}, keywords = {dblp}, number = 11, pages = {1-20}, timestamp = {2016-02-02T06:12:02.000+0100}, title = {Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.}, url = {http://dblp.uni-trier.de/db/journals/chinaf/chinaf56.html#WangLYZCYW13}, volume = 56, year = 2013 }