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%0 Journal Article
%1 journals/iet-cds/ArnaldoRAH12
%A Arnaldo, Ignacio
%A Risco-Martín, José Luis
%A Ayala, José Luis
%A Hidalgo, José Ignacio
%D 2012
%J IET Circuits, Devices & Systems
%K dblp
%N 5
%P 322-329
%T Power profiling-guided floorplanner for 3D multi-processor systems-on-chip.
%U http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds6.html#ArnaldoRAH12
%V 6
@article{journals/iet-cds/ArnaldoRAH12,
added-at = {2018-11-14T00:00:00.000+0100},
author = {Arnaldo, Ignacio and Risco-Martín, José Luis and Ayala, José Luis and Hidalgo, José Ignacio},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c5b8a6d39dfd9954593e0e20dc7252c2/dblp},
ee = {https://www.wikidata.org/entity/Q57698169},
interhash = {6d67208190d2585397258a9c975c84e2},
intrahash = {c5b8a6d39dfd9954593e0e20dc7252c2},
journal = {IET Circuits, Devices & Systems},
keywords = {dblp},
number = 5,
pages = {322-329},
timestamp = {2019-09-27T07:24:11.000+0200},
title = {Power profiling-guided floorplanner for 3D multi-processor systems-on-chip.},
url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds6.html#ArnaldoRAH12},
volume = 6,
year = 2012
}
