%0 Conference Paper %1 conf/vlsid/MinPP11 %A Min, Su Myat %A Peddersen, Jorgen %A Parameswaran, Sri %B VLSI Design %D 2011 %I IEEE Computer Society %K dblp %P 141-146 %T Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2011.html#MinPP11 %@ 978-0-7695-4348-2

@inproceedings{conf/vlsid/MinPP11, added-at = {2015-04-20T00:00:00.000+0200}, author = {Min, Su Myat and Peddersen, Jorgen and Parameswaran, Sri}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2682974fd4436fe69f30e9119d1167b14/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2011}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2011.36}, interhash = {59dce2e39f2324adec40dd45ec0c891b}, intrahash = {682974fd4436fe69f30e9119d1167b14}, isbn = {978-0-7695-4348-2}, keywords = {dblp}, pages = {141-146}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T11:08:32.000+0100}, title = {Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2011.html#MinPP11}, year = 2011 }