%0 Conference Paper %1 conf/vlsic/LeeSTKMSSKB15 %A Lee, Sang Min %A Seo, Dongwon %A Taleie, Shahin Mehdizad %A Kong, Derui %A McGowan, Michael Joseph %A Song, Tongyu %A Saripalli, Ganesh R. %A Kuo, Jenny %A Bazarjani, Seyfi S. %B VLSIC %D 2015 %I IEEE %K dblp %P 164- %T A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2015.html#LeeSTKMSSKB15 %@ 978-4-86348-502-0

@inproceedings{conf/vlsic/LeeSTKMSSKB15, added-at = {2016-03-16T00:00:00.000+0100}, author = {Lee, Sang Min and Seo, Dongwon and Taleie, Shahin Mehdizad and Kong, Derui and McGowan, Michael Joseph and Song, Tongyu and Saripalli, Ganesh R. and Kuo, Jenny and Bazarjani, Seyfi S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2868ec94fc458b947046d60f949b4e439/dblp}, booktitle = {VLSIC}, crossref = {conf/vlsic/2015}, ee = {http://dx.doi.org/10.1109/VLSIC.2015.7231251}, interhash = {57d45ac498e412713cf76fa9bc12d787}, intrahash = {868ec94fc458b947046d60f949b4e439}, isbn = {978-4-86348-502-0}, keywords = {dblp}, pages = {164-}, publisher = {IEEE}, timestamp = {2016-03-17T10:33:18.000+0100}, title = {A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2015.html#LeeSTKMSSKB15}, year = 2015 }