%0 Journal Article %1 journals/ieicet/YangDLN13 %A Yang, Bo %A Dong, Qing %A Li, Jing %A Nakatake, Shigetoshi %D 2013 %J IEICE Transactions %K dblp %N 12 %P 2475-2486 %T Structured Analog Circuit and Layout Design with Transistor Array. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet96a.html#YangDLN13 %V 96-A

@article{journals/ieicet/YangDLN13, added-at = {2018-09-28T00:00:00.000+0200}, author = {Yang, Bo and Dong, Qing and Li, Jing and Nakatake, Shigetoshi}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2902106a08250080aef5e1068e7aa59b5/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e96-a_12_2475}, interhash = {4e4e363c66b9043d8d3fd1b63a940867}, intrahash = {902106a08250080aef5e1068e7aa59b5}, journal = {IEICE Transactions}, keywords = {dblp}, number = 12, pages = {2475-2486}, timestamp = {2019-09-27T07:15:07.000+0200}, title = {Structured Analog Circuit and Layout Design with Transistor Array.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet96a.html#YangDLN13}, volume = {96-A}, year = 2013 }