%0 Journal Article %1 journals/jssc/ZhangTSK14 %A Zhang, Sai %A Tu, Jane S. %A Shanbhag, Naresh R. %A Krein, Philip T. %D 2014 %J J. Solid-State Circuits %K dblp %N 11 %P 2644-2657 %T A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#ZhangTSK14 %V 49

@article{journals/jssc/ZhangTSK14, added-at = {2014-11-18T00:00:00.000+0100}, author = {Zhang, Sai and Tu, Jane S. and Shanbhag, Naresh R. and Krein, Philip T.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/218da8b456b610c87c4bcd62704a42ee0/dblp}, ee = {http://dx.doi.org/10.1109/JSSC.2014.2354048}, interhash = {4e3f9fdd246744c56e0c0f3da54bbf06}, intrahash = {18da8b456b610c87c4bcd62704a42ee0}, journal = {J. Solid-State Circuits}, keywords = {dblp}, number = 11, pages = {2644-2657}, timestamp = {2016-02-02T09:37:00.000+0100}, title = {A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#ZhangTSK14}, volume = 49, year = 2014 }