%0 Journal Article %1 journals/tjs/GaoWXYLQZC18 %A Gao, Lan %A Wang, Rui %A Xu, Yunlong %A Yang, Hailong %A Luan, Zhongzhi %A Qian, Depei %A Zhang, Han %A Cai, Jihong %D 2018 %J The Journal of Supercomputing %K dblp %N 7 %P 3388-3414 %T SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures. %U http://dblp.uni-trier.de/db/journals/tjs/tjs74.html#GaoWXYLQZC18 %V 74

@article{journals/tjs/GaoWXYLQZC18, added-at = {2018-08-11T00:00:00.000+0200}, author = {Gao, Lan and Wang, Rui and Xu, Yunlong and Yang, Hailong and Luan, Zhongzhi and Qian, Depei and Zhang, Han and Cai, Jihong}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2453e57d328ab3ced08de75d2b0957a76/dblp}, ee = {https://doi.org/10.1007/s11227-018-2389-3}, interhash = {450cb24a630d37a9f17b205dc9468ddf}, intrahash = {453e57d328ab3ced08de75d2b0957a76}, journal = {The Journal of Supercomputing}, keywords = {dblp}, number = 7, pages = {3388-3414}, timestamp = {2019-09-27T06:53:47.000+0200}, title = {SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.}, url = {http://dblp.uni-trier.de/db/journals/tjs/tjs74.html#GaoWXYLQZC18}, volume = 74, year = 2018 }