%0 Journal Article %1 journals/jssc/WallingLPRDSA09 %A Walling, Jeffrey S. %A Lakdawala, Hasnain %A Palaskas, Yorgos %A Ravi, Ashoke %A Degani, Ofir %A Soumyanath, Krishnamurthy %A Allstot, David J. %D 2009 %J J. Solid-State Circuits %K dblp %N 6 %P 1668-1678 %T A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#WallingLPRDSA09 %V 44

@article{journals/jssc/WallingLPRDSA09, added-at = {2019-09-25T00:00:00.000+0200}, author = {Walling, Jeffrey S. and Lakdawala, Hasnain and Palaskas, Yorgos and Ravi, Ashoke and Degani, Ofir and Soumyanath, Krishnamurthy and Allstot, David J.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/20170fcbec9969edcf34b40480aaf7c84/dblp}, ee = {https://doi.org/10.1109/JSSC.2009.2020205}, interhash = {40082660c5c2fb7a92c3338532463a2f}, intrahash = {0170fcbec9969edcf34b40480aaf7c84}, journal = {J. Solid-State Circuits}, keywords = {dblp}, number = 6, pages = {1668-1678}, timestamp = {2019-09-27T06:09:34.000+0200}, title = {A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#WallingLPRDSA09}, volume = 44, year = 2009 }