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%0 Journal Article
%1 journals/jssc/NuytsSDRD12
%A Nuyts, Pieter A. J.
%A Singerl, Peter
%A Dielacher, Franz
%A Reynaert, Patrick
%A Dehaene, Wim
%D 2012
%J J. Solid-State Circuits
%K dblp
%N 7
%P 1681-1692
%T A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc47.html#NuytsSDRD12
%V 47
@article{journals/jssc/NuytsSDRD12,
added-at = {2018-11-02T00:00:00.000+0100},
author = {Nuyts, Pieter A. J. and Singerl, Peter and Dielacher, Franz and Reynaert, Patrick and Dehaene, Wim},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2fe3aef3abfa777ce2a6e9d6a221110b6/dblp},
ee = {https://doi.org/10.1109/JSSC.2012.2191032},
interhash = {34ea940a8a266f745861c94a1ba562c1},
intrahash = {fe3aef3abfa777ce2a6e9d6a221110b6},
journal = {J. Solid-State Circuits},
keywords = {dblp},
number = 7,
pages = {1681-1692},
timestamp = {2019-09-27T06:09:29.000+0200},
title = {A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc47.html#NuytsSDRD12},
volume = 47,
year = 2012
}