%0 Journal Article %1 journals/tcas/NarasimhanS10 %A Narasimhan, Ashok %A Sridhar, Ramalingam %D 2010 %J IEEE Trans. on Circuits and Systems %K dblp %N 12 %P 3055-3063 %T Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI57.html#NarasimhanS10 %V 57-I

@article{journals/tcas/NarasimhanS10, added-at = {2011-10-19T00:00:00.000+0200}, author = {Narasimhan, Ashok and Sridhar, Ramalingam}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2782b1e60b7a15e6ea116bebdf991612b/dblp}, ee = {http://dx.doi.org/10.1109/TCSI.2010.2073790}, interhash = {332217f3ed65ff8f6db3759afd15eebb}, intrahash = {782b1e60b7a15e6ea116bebdf991612b}, journal = {IEEE Trans. on Circuits and Systems}, keywords = {dblp}, number = 12, pages = {3055-3063}, timestamp = {2016-02-02T02:22:12.000+0100}, title = {Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI57.html#NarasimhanS10}, volume = {57-I}, year = 2010 }