%0 Journal Article %1 journals/tdsc/MeixnerS09 %A Meixner, Albert %A Sorin, Daniel J. %D 2009 %J IEEE Trans. Dependable Sec. Comput. %K dblp %N 1 %P 18-31 %T Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. %U http://dblp.uni-trier.de/db/journals/tdsc/tdsc6.html#MeixnerS09 %V 6

@article{journals/tdsc/MeixnerS09, added-at = {2016-03-03T00:00:00.000+0100}, author = {Meixner, Albert and Sorin, Daniel J.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/285b36d9404904f0badcefd26c3cac362/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TDSC.2007.70243}, interhash = {2ff3b34abcf652fc76ddea205e1b1aa5}, intrahash = {85b36d9404904f0badcefd26c3cac362}, journal = {IEEE Trans. Dependable Sec. Comput.}, keywords = {dblp}, number = 1, pages = {18-31}, timestamp = {2016-03-04T10:32:00.000+0100}, title = {Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.}, url = {http://dblp.uni-trier.de/db/journals/tdsc/tdsc6.html#MeixnerS09}, volume = 6, year = 2009 }