%0 Conference Paper %1 conf/iscas/Rodriguez-VillegasQAR02 %A Rodríguez-Villegas, Esther %A Quintana, José M. %A Avedillo, Maria J. %A Rueda, Adoración %B ISCAS (5) %D 2002 %I IEEE %K dblp %P 389-392 %T High-speed low-power logic gates using floating gates. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2002-5.html#Rodriguez-VillegasQAR02 %@ 0-7803-7448-7

@inproceedings{conf/iscas/Rodriguez-VillegasQAR02, added-at = {2016-05-20T00:00:00.000+0200}, author = {Rodríguez-Villegas, Esther and Quintana, José M. and Avedillo, Maria J. and Rueda, Adoración}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/25c26db52dae12cd58ee81ac876e3466e/dblp}, booktitle = {ISCAS (5)}, crossref = {conf/iscas/2002}, ee = {http://dx.doi.org/10.1109/ISCAS.2002.1010722}, interhash = {280bcaba1c993a1cec40c20551534929}, intrahash = {5c26db52dae12cd58ee81ac876e3466e}, isbn = {0-7803-7448-7}, keywords = {dblp}, pages = {389-392}, publisher = {IEEE}, timestamp = {2016-05-21T09:38:49.000+0200}, title = {High-speed low-power logic gates using floating gates.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2002-5.html#Rodriguez-VillegasQAR02}, year = 2002 }