%0 Journal Article %1 journals/dafes/VasudevanVAT08 %A Vasudevan, Shobha %A Viswanath, Vinod %A Abraham, Jacob A. %A Tu, Jiajin %D 2008 %J Design Autom. for Emb. Sys. %K dblp %N 4 %P 377-396 %T Sequential equivalence checking between system level and RTL descriptions. %U http://dblp.uni-trier.de/db/journals/dafes/dafes12.html#VasudevanVAT08 %V 12

@article{journals/dafes/VasudevanVAT08, added-at = {2011-11-29T00:00:00.000+0100}, author = {Vasudevan, Shobha and Viswanath, Vinod and Abraham, Jacob A. and Tu, Jiajin}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/25261aac17cc9a3d205e2ceaec554630d/dblp}, ee = {http://dx.doi.org/10.1007/s10617-008-9033-z}, interhash = {224e005216c8216fae4abce254f2f396}, intrahash = {5261aac17cc9a3d205e2ceaec554630d}, journal = {Design Autom. for Emb. Sys.}, keywords = {dblp}, number = 4, pages = {377-396}, timestamp = {2016-02-02T05:55:41.000+0100}, title = {Sequential equivalence checking between system level and RTL descriptions.}, url = {http://dblp.uni-trier.de/db/journals/dafes/dafes12.html#VasudevanVAT08}, volume = 12, year = 2008 }