%0 Conference Paper %1 conf/vlsid/KumarV18 %A Kumar, Ashish %A Visweswaran, G. S. %B VLSI Design %D 2018 %I IEEE Computer Society %K dblp %P 261-265 %T A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2018.html#KumarV18 %@ 978-1-5386-3692-3

@inproceedings{conf/vlsid/KumarV18, added-at = {2018-04-10T00:00:00.000+0200}, author = {Kumar, Ashish and Visweswaran, G. S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/20bb6c2bcfaf11e0ad8d53b7888fd6308/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2018}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2018.73}, interhash = {219171c6107ee521fa1de494904118f8}, intrahash = {0bb6c2bcfaf11e0ad8d53b7888fd6308}, isbn = {978-1-5386-3692-3}, keywords = {dblp}, pages = {261-265}, publisher = {IEEE Computer Society}, timestamp = {2019-09-27T18:12:18.000+0200}, title = {A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2018.html#KumarV18}, year = 2018 }