%0 Conference Paper %1 conf/date/KlingaufGG06 %A Klingauf, Wolfgang %A Gädke, Hagen %A Günzel, Robert %B DATE %D 2006 %E Gielen, Georges G. E. %I European Design and Automation Association, Leuven, Belgium %K dblp %P 1318-1323 %T TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC. %U http://dblp.uni-trier.de/db/conf/date/date2006p.html#KlingaufGG06 %@ 3-9810801-1-4

@inproceedings{conf/date/KlingaufGG06, added-at = {2015-11-11T00:00:00.000+0100}, author = {Klingauf, Wolfgang and Gädke, Hagen and Günzel, Robert}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2a9b5a785258159ff6b6d0752c8194bd0/dblp}, booktitle = {DATE}, crossref = {conf/date/2006p}, editor = {Gielen, Georges G. E.}, ee = {http://dl.acm.org/citation.cfm?id=1131843}, interhash = {2011ca9ce6ae8bcbf67cc7e7e57cc736}, intrahash = {a9b5a785258159ff6b6d0752c8194bd0}, isbn = {3-9810801-1-4}, keywords = {dblp}, pages = {1318-1323}, publisher = {European Design and Automation Association, Leuven, Belgium}, timestamp = {2016-02-02T13:23:37.000+0100}, title = {TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC.}, url = {http://dblp.uni-trier.de/db/conf/date/date2006p.html#KlingaufGG06}, year = 2006 }