%0 Conference Paper %1 conf/vlsid/DesaiNKPVK10 %A Desai, Kunal %A Nagulapalli, Rajasekhar %A Krishna, Vijay %A Palwai, Rajkumar %A Venkatesan, Pravin Kumar %A Khawshe, Vijay %B VLSI Design %D 2010 %I IEEE Computer Society %K dblp %P 300-305 %T High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#DesaiNKPVK10 %@ 978-0-7695-3928-7

@inproceedings{conf/vlsid/DesaiNKPVK10, added-at = {2015-04-20T00:00:00.000+0200}, author = {Desai, Kunal and Nagulapalli, Rajasekhar and Krishna, Vijay and Palwai, Rajkumar and Venkatesan, Pravin Kumar and Khawshe, Vijay}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/242df904b44af38fa3d58e9276f7c1e68/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2010}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.104}, interhash = {1c65c25438a3d288ce830f1576e4e303}, intrahash = {42df904b44af38fa3d58e9276f7c1e68}, isbn = {978-0-7695-3928-7}, keywords = {dblp}, pages = {300-305}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T11:08:48.000+0100}, title = {High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#DesaiNKPVK10}, year = 2010 }