%0 Conference Paper %1 conf/date/VeredasSP06 %A Veredas, Francisco-Javier %A Scheppler, Michael %A Pfleiderer, Hans-Jörg %B DATE Designers' Forum %D 2006 %E Gielen, Georges G. E. %I European Design and Automation Association, Leuven, Belgium %K dblp %P 36-41 %T Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. %U http://dblp.uni-trier.de/db/conf/date/date2006.html#VeredasSP06 %@ 3-9810801-0-6

@inproceedings{conf/date/VeredasSP06, added-at = {2015-11-11T00:00:00.000+0100}, author = {Veredas, Francisco-Javier and Scheppler, Michael and Pfleiderer, Hans-Jörg}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2f1bcdf7415f811eef0d4bdd27c16178e/dblp}, booktitle = {DATE Designers' Forum}, crossref = {conf/date/2006}, editor = {Gielen, Georges G. E.}, ee = {http://dl.acm.org/citation.cfm?id=1131364}, interhash = {14b3991f65d4dce9613b2b7da8927a30}, intrahash = {f1bcdf7415f811eef0d4bdd27c16178e}, isbn = {3-9810801-0-6}, keywords = {dblp}, pages = {36-41}, publisher = {European Design and Automation Association, Leuven, Belgium}, timestamp = {2016-02-02T13:24:08.000+0100}, title = {Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.}, url = {http://dblp.uni-trier.de/db/conf/date/date2006.html#VeredasSP06}, year = 2006 }