%0 Conference Paper %1 conf/glvlsi/SunLZMZ11 %A Sun, Hongbin %A Liu, Chuanyin %A Zheng, Nanning %A Min, Tai %A Zhang, Tong %B ACM Great Lakes Symposium on VLSI %D 2011 %E Atienza, David %E Xie, Yuan %E Ayala, José L. %E Stevens, Ken S. %I ACM %K dblp %P 97-102 %T Design techniques to improve the device write margin for MRAM-based cache memory. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2011.html#SunLZMZ11 %@ 978-1-4503-0667-6

@inproceedings{conf/glvlsi/SunLZMZ11, added-at = {2018-11-06T00:00:00.000+0100}, author = {Sun, Hongbin and Liu, Chuanyin and Zheng, Nanning and Min, Tai and Zhang, Tong}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/27a8624ac36b248390d82592fe3f3d0d7/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2011}, editor = {Atienza, David and Xie, Yuan and Ayala, José L. and Stevens, Ken S.}, ee = {https://doi.org/10.1145/1973009.1973030}, interhash = {0f1480bb9a97f9c3265f04ce2f4ab662}, intrahash = {7a8624ac36b248390d82592fe3f3d0d7}, isbn = {978-1-4503-0667-6}, keywords = {dblp}, pages = {97-102}, publisher = {ACM}, timestamp = {2019-09-27T19:33:36.000+0200}, title = {Design techniques to improve the device write margin for MRAM-based cache memory.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2011.html#SunLZMZ11}, year = 2011 }