%0 Journal Article %1 journals/jssc/IntiYESH11 %A Inti, Rajesh %A Yin, Wenjing %A Elshazly, Amr %A Sasidhar, Naga %A Hanumolu, Pavan Kumar %D 2011 %J J. Solid-State Circuits %K dblp %N 12 %P 3150-3162 %T A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. %U http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#IntiYESH11 %V 46

@article{journals/jssc/IntiYESH11, added-at = {2011-12-02T00:00:00.000+0100}, author = {Inti, Rajesh and Yin, Wenjing and Elshazly, Amr and Sasidhar, Naga and Hanumolu, Pavan Kumar}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/28ab120ef95163f8443b9ea025564d207/dblp}, ee = {http://dx.doi.org/10.1109/JSSC.2011.2168872}, interhash = {064c961a2b254a523b965a56a721f7d9}, intrahash = {8ab120ef95163f8443b9ea025564d207}, journal = {J. Solid-State Circuits}, keywords = {dblp}, number = 12, pages = {3150-3162}, timestamp = {2016-02-02T09:37:10.000+0100}, title = {A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#IntiYESH11}, volume = 46, year = 2011 }