PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Roussel, Philippe"

Author of the publication

copydeleteadd this publication to your clipboard
Implementation of new monitoring tools and optimisation of maintenance through the use of Webbased technology

, , , , , and . (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jun. -Prof. Dr. Philippe Grönquist University of Stuttgart

 

Other publications of authors with the same name

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability., , , , , , , , , and 4 other author(s). Microelectronics Reliability, (2018)Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications., , , , , , and . ESSDERC, page 62-65. IEEE, (2018)Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations., , , , and . CODES+ISSS, page 253-258. ACM, (2006)Method to assess the impact of LER and spacing variation on BEOL dielectric reliability using 2D-field simulations for <20nm spacing., , , , , and . IRPS, page 10-1. IEEE, (2018)The defect-centric perspective of device and circuit reliability - From individual defects to circuits., , , , , , , , , and 5 other author(s). ESSDERC, page 218-225. IEEE, (2015)Stochastic Modeling of Hot-Carrier Degradation in nFinFETs Considering the Impact of Random Traps and Random Dopants., , , , , , , , , and 1 other author(s). ESSDERC, page 262-265. IEEE, (2019)Exponent Monte Carlo for Quick Statistical Circuit Simulation., , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 36-45. Springer, (2009)Variability aware modeling for yield enhancement of SRAM and logic., , , and . DATE, page 1153-1158. IEEE, (2011)Editing First-Order Proofs: Programmed Rules vs Derived Rules., , and . SLP, page 92-98. IEEE-CS, (1984)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies., , , , , , , , , and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)