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A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS., , , , , , , , and . ISSCC, page 180-182. IEEE, (2012)Experiences in Applying Formal Verification in Robotics., , and . SAFECOMP, volume 6351 of Lecture Notes in Computer Science, page 347-360. Springer, (2010)Parametrized Exceptions., , and . CALCO, volume 3629 of Lecture Notes in Computer Science, page 424-438. Springer, (2005)Exploiting transistor-level reconfiguration to optimize combinational circuits., , , , , , and . DATE, page 338-343. IEEE, (2017)Integration of a security type system into a program logic., , , and . Theor. Comput. Sci., 402 (2-3): 172-189 (2008)A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology., , , , , and . IEEE Trans. VLSI Syst., 21 (3): 566-570 (2013)Guaranteeing functional safety: design for provability and computer-aided verification., , , , , , and . Auton. Robots, 32 (3): 303-331 (2012)A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs., , , , , , , , , and . DATE, page 605-608. IEEE, (2018)A formal verification environment for use in the certification of safety-related C-programs.. University of Bremen, (2010)On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links., , , and . IJERTCS, 3 (4): 42-56 (2012)