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Performance debugging of Esterel specifications., , , and . Real-Time Systems, 48 (5): 570-600 (2012)Inductively Verifying Invariant Properties of Parameterized Systems., and . Autom. Softw. Eng., 11 (2): 101-139 (2004)Automatic Generation of Protocol Converters from Scenario-Based Specifications., , , and . RTSS, page 447-458. IEEE Computer Society, (2004)Generalized Unfold/fold Transformation Systems for Normal Logic Programs., , and . ICLP, page 616. MIT Press, (1999)A Conservative Technique to Improve Deterministic Evaluation of Logic Programs., , , and . ICCL, page 196-205. IEEE Computer Society, (1998)BesFS: Mechanized Proof of an Iago-Safe Filesystem for Enclaves., , , , , and . CoRR, (2018)A Retargetable Software Timing Analyzer Using Architecture Description Language., , , , and . ASP-DAC, page 396-401. IEEE Computer Society, (2007)Using Compressed Bytecode Traces for Slicing Java Programs., and . ICSE, page 512-521. IEEE Computer Society, (2004)Scalable and precise refinement of cache timing analysis via path-sensitive verification., and . Real-Time Systems, 49 (4): 517-562 (2013)Static analysis of multi-core TDMA resource arbitration delays., , , , and . Real-Time Systems, 50 (2): 185-229 (2014)