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The structure of chips and links comprising the IBM eServer z990 I/O subsystem., , , , , , , , , and 3 other author(s). IBM Journal of Research and Development, 48 (3-4): 449-460 (2004)Design and verification of the IBM System z10 I/O subsystem chips., , , , , , , , , and 1 other author(s). IBM Journal of Research and Development, 53 (1): 7 (2009)IBM System z10 I/O subsystem., , , , , , , , , and 4 other author(s). IBM Journal of Research and Development, 53 (1): 6 (2009)Task-accurate performance modeling in SystemC for real-time multi-processor architectures., , , , , and . DATE, page 480-481. European Design and Automation Association, Leuven, Belgium, (2006)S/390 Parallel Enterprise Server Generation 3: A balanced system and cache structure., , , , , , , and . IBM Journal of Research and Development, 41 (4&5): 405-428 (1997)Formal verification made easy., , , , and . IBM Journal of Research and Development, 41 (4&5): 567-576 (1997)Event monitoring in highly complex hardware systems., , , , , , , and . IBM Journal of Research and Development, 43 (5): 889-898 (1999)