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An electrical-aware parametric DFM solution for analog circuits., , , , , , , and . IDT, page 68-73. IEEE, (2011)Exploiting satisfiability modulo theories for analog layout automation., , , , , and . IDT, page 1-6. IEEE, (2014)Incremental layout-aware analog design methodology., and . ICECS, page 486-489. IEEE, (2015)PLL Real Number Modeling in SystemVerilog., , and . SMACD, page 257-260. IEEE, (2019)System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation., , , and . MTV, page 55-60. IEEE, (2014)Design of a low-power ZigBee receiver front-end for wireless sensors., , and . Microelectronics Journal, 40 (11): 1561-1568 (2009)Systematic design and optimization of operational transconductance amplifier using gm/ID design methodology., , and . Microelectronics Journal, (2018)Forty years of Computers & Industrial Engineering: A bibliometric analysis., , , , and . Computers & Industrial Engineering, (2017)Chameleon ART: a non-optimization based analog design migration framework., , , , , , , and . DAC, page 885-888. ACM, (2006)A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation., , and . IDT, page 44-48. IEEE, (2015)